1. Technical Field
The present disclosure relates to a testing method for semiconductor integrated electronic devices.
More specifically the disclosure relates to a testing method for at least one device DUT provided with an integrated testing circuit and connected to at least one tester ATE.
The disclosure also relates to a testing architecture for implementing this testing method.
The disclosure particularly, but not exclusively, relates to the testing methods for the processes of electric selection of the wafers and the following description is made with reference to this field of application by way of illustration only.
2. Description of the Related Art
As it is well known, the process of electric selection of devices executed on wafers, i.e., the so called testing EWS (acronym of “Electrical-Wafer-Sorting”), involves electrically connecting a tester or ATE (acronym of “Automatic Test Equipment”) which executed measurements on a wafer whereon electronic components are present to be verified or selected or tested, in particular chips, generically indicated as devices DUT (acronym of “Device Under Test”). A portion of a testing system is schematically shown in FIG. 1, globally indicated with 1.
The interface between a real tester ATE 2 and a wafer 8 comprising a plurality of devices to be tested or selected, in particular chips (also indicated as integrated circuits or IC, acronym of “Integrated Circuit”) is a so called probe card 4, which is a board substantially made of a PCB (acronym of “Printed Circuit Board”) and of a probe head 5 which comprises different hundreds (often thousands) of probes 6 which electrically connect the tester ATE 2 with almost all the contact pads 7 of a device DUT to be tested.
Moreover, an interface or testing board 3 can be interposed, as in the case shown in FIG. 1, between the tester ATE 2 and the probe card 4. In particular, the testing board 3 usually comprises additional circuits for the testing of the at least one device DUT.
In general, the wafer 8 groups a plurality of devices DUT to be tested, and during the testing steps it is placed on a support called chuck 9, shown in the portion of the testing system 1, and belonging to an apparatus called prober (not shown in the figure), this support being then also indicated as prober chuck.
The number of pads 7 for a determined testing can be lower than or identical to the total number of pads present on the device DUT to be tested.
The process goes ahead in a similar way even if on the devices DUT or chips contact bumps (or projecting protuberances) are present instead of pads, as it is well known to the skilled in the art.
In particular, all the pads 7 of the device or of the devices DUT (in the more and more frequent case of parallel testing of more devices simultaneously), for the testing are to be connected to the ATE, but generally almost all the pads present on the device/devices DUT are used as schematically shown in FIG. 2.
Before each chip is encapsulated in a relative package, the testing of the chip itself still on the wafer 8 is then executed, by using the probes 6 that are directly connected to the pads 7 of the chip and that thus execute the so called probing of the pads 7 they come in contact with.
After the testing, the wafer 8 is cut and the chips to be proved to be in working order are assembled in their package, ready for further process steps, also comprising final testing steps in the package wherein they have been assembled.
In a way similar to the testing on wafer, the tester ATE is in particular able to executed a final test or FT (acronym of “Final Test”) of what is contained in the package comprising a given chip, electrically contacting the connections of the same package itself.
In the case of systems SiP (acronym of “System In Package”) other situations may occur, even very complex, further to the creation of electric connections between the various parts (chips, passive components, PCB, . . . ) of the system, these situations being known to the technicians of the field and in particular to the testing experts.
Such a testing apparatus can be used also for the test WLBI (Wafer Level Burn-In) i.e., electric testing which is executed on the chips of the tests (also at high temperature) stress being present.
The process goes ahead in a similar way also for a generic electronic system, however complex, where this system is connected to the ATE that tests its functionalities, and the ATE connects itself to the resources of the system, and these connections are made available by the system through pads (for the chips on wafer), bumps (for the chips on wafer or encapsulated in a package) or more in general with suitable connectors, that will be hereafter in any case called resources.
It is also known that for the testing of the digital part of the DUT or digital circuit it is convenient to use scanning techniques, based on scan chain and ATPG (acronym of “Advanced Test Pattern Generator”). In particular, considering a generic logic network with combinatorial and sequential elements, the scan chains are created by replacing the flip flops FF of this logic network with scan flip flops FF at whose input a suitable circuit is placed which in general is a multiplexer able to create the scan chains desired when the testing step of the digital circuit is being executed. This testing step is generally called test mode, for distinguishing it from the normal operation of the circuit, indicated indifferently as user mode, normal mode or normal.
A control signal is used for switching the device DUT from the user mode configuration to the test mode configuration, so that in the digital circuit the generic scan chain is created which is, in practice, a shift register that groups at least one part of the memory elements (flip flops) of the digital circuit of the device DUT.
More in particular, the test scan chains of the digital circuit of the device DUT in test mode configuration are pre-charged with suitable values and for testing the correct operation of the digital circuit itself. These values are indifferently called testing vectors, scan vectors or test vectors.
Thanks to this, the number of combinations the input signals have to take in order to demonstrate the correct functionality of the digital circuit itself is significantly reduced, verifying for each input combination, that the value of the outputs is correct.
In practice, the scan chains are pre-charged with the test vectors, that are then applied to a combinatorial network which is connected to the outputs of the various flip-flops of the scan chains themselves. During the application of the test vectors to the combinatorial network also the main input values or stimuli PI (acronym of: “Primary Inputs”) of the digital circuit are set.
Against these stimuli PI, and the test vectors pre-charged in the scan chains, the outputs of the combinatorial network and the memory elements (flip flops) of the scan chains will take a certain value, indicated also as signatures.
The output signatures are then discharged by the scan chains and also the output values PO (acronym of: “Primary Outputs”) are read, which are then compared with the ATE 2 with the awaited values so as to demonstrate the correct functionality of the digital circuit.
In substance, it is the tester ATE 2 that always supplies at the input of the digital circuit of the DUT and charges the test vectors and also discharges the output signatures and analyses them. At present, between the tester ATE and the at least one device DUT there exists a bidirectional exchange of information through signals that go from the ATE 2 to the device DUT and vice versa.
The number of flip flops present in the scan chains and the number of scan chains obviously determines the time for charging the test vectors and discharging the output signatures.
In consequence, if the scan chains are little deep (i.e., they comprise a limited number of flip flops) the test time is reduced. In any case, it is to be taken into account that the testers ATE have a limited number of digital channels or resources to which the scan chains can be connected, and this number of resources determines the number of scan chains that can be created in the digital circuit.
It is then known to use techniques of compression or scan compression for reducing the depth of the scan chains, increasing at the same time the number of scan chains themselves.
For executing the testing through scan compression two suitable circuits are placed at the input and at the output of the scan chains, the first circuit executing the decompression of the test vectors at the input of the scan chains, and the second circuit executing the compression of the output signatures of the scan chains.
In consequence the ATE 2 supplies at the input the compressed test vectors and collects at the output the compressed output signatures.
Thanks to the scan compression a compression factor equal to ten or higher is obtained according to the particular circuit considered.
The test vectors and the output signatures are usually generated by a suitable software tool called ATPG (acronym of “Advanced Test Pattern Generator”), that, in its upgraded versions, supplies also the compressed test vectors and output signatures.
The compression of the output signatures can also be replaced with their compaction. For example for the compaction of the signature a MISR (Multiple Input Shift Register) can be used.
The compression differs from the compaction in that with the compression there is no loss of information (and thus the original response of the digital circuit in question can be reconstructed), while with the compaction there is loss of information (and thus the original response of the circuit itself cannot be reconstructed).
In a known way, there can also be unknown states generally indicated with X. It is important to avoid the propagation of these unknown states since they can alter the corresponding output signatures. This propagation block is in particular obtained by means of techniques and circuits that mask and/or block the sources that generate these unknown states, exactly avoiding their propagation.
Devices DUT are also known also provided with integrated self-test circuits or systems of the BIST type (acronym of “Built In Self Test”), especially used in the case of test of the relative digital circuits, as the system shown in FIG. 3, globally indicated with 10.
In particular, during its normal operation, the device DUT 10 does not use its self-test circuits BIST and communicates with the external world through the inputs PI and the outputs PO, while during a test mode the self-test circuits BIST are activated.
The device DUT 10 is in particular provided with a digital portion or digital circuit 11 as well as with self-test circuitry, in particular comprising a generator block (i.e., a suitable circuit) 12 or test pattern generator (TPG) which automatically generates the test vectors that are applied at the input of the digital circuit 11, while its output signatures are brought to a further block, in particular an analyzer block 13 or block ORA (acronym of “Output Response Analyzer) that compacts and/or compresses them and compares them with the awaited compacted and/or compressed signatures, contained in the testing system.
All the test operations are however controlled by a controller 14 indicated as BIST controller that supplies at the output a result of the binary test, which takes the values Good (for a test that has been successful) or Fail (for a failure of the test). Normally, a multiplexer Mux is interposed between the block generator 12 and the digital circuit 11.
The controller 14 receives in particular a switch signal for the choice of the operation mode of the device DUT 10, between a normal mode and a test mode as above described and supplies then at the input of the digital circuit 11a reconfiguration signal Reconf.
In particular, the generator block 12 generates the test vectors and transmits them, through the multiplexer Mux to the digital circuit 11. In the analyzer block 13 suitable memory banks or in any case an algorithmic circuit are provided wherein the signatures awaited from digital circuit 11 are wired: the analyzer block 13 compares the response of the digital circuit 11, in response to the input stimuli, with these memorized signatures and transmits the result to the controller 14.
It is to be noted that both the generator block 12 and the analyzer block 13 are wired and thus difficult to be changed.
Further circuits for the diagnosis of the failure can be considered.
Also in the case of BIST circuits attention should be paid to the unknown states, for obtaining in any case strong circuits, indicated as X-tolerant circuits.
It is also known to execute the testing of at least one integrated circuit by using radiofrequency signals RF possibly overlapped onto a supply line or power line. Alternatively, these signals RF can be exchanged through electromagnetic waves by using a wireless channel.
In particular, the signals RF are received or transmitted by using transceiver/transponder blocks, which in the case of a wireless communication channel are connected to antennas that can be of various types, for example with magnetic dipole or with hertzian dipole or of the capacitive type or else.
The vastness of the cases considered implies that the testing of a device DUT integrated on a wafer is often faced case by case studying a suitable technique of DFT (acronym of “Design For Test”) to be applied to the specific device DUT according to a precise type of tester ATE.
The growing complexity of the integrated circuits and the limited resources of a generic tester ATE often do not allow however to have high testing parallelisms, and this increases the costs of the testing itself.
Moreover, the high complexity implies a high information exchange between the tester ATE and the device DUT, which further complicates the architecture of the tester ATE, increasing its cost, for example requiring big size memories.
In the case of testing using signals overlapped onto the power line or through a wireless communication channel, also the device DUT gets complicated due to the presence therein of suitable transceiver/transponder blocks (indicated also as RxTx).
The classical approach thus consists in applying the techniques of DFT to a single device DUT, since it is repeated as it is on the whole wafer whose testing is to be executed, and this testing consists in the bidirectional exchange of information between the tester ATE and the device DUT.